David C Black’s World



e-mail: dcblack@ieee.org

Austin, TX 78749-1838


A well known ESL (Electronic System Level design) consultant and teacher, David has successfully created reusable components using advanced methodologies, and appropriate design automation techniques. System level designs described with executable specifications that enabled first time success on many digital design projects. With a diversity of hardware and software backgrounds, I have successfully integrated new electronic design automation (EDA) tools, and improved methodology while mentoring team members. David has received recognition as an excellent teacher from students who were taught effective technology and techniques for modeling implementation and verification.


Strong understanding of the entire ASIC design process from specification through verification, implementation, synthesis, layout and test generation. An excellent understanding of methodologies. This includes a deep understanding of verification and implementation in multiple technologies. Good communications and writing skills. Effective team member, student and teacher. Enjoy teaching. Able to handle basic system administration tasks and establish secure communications. On-the-job proficiency with multiple EDA tools. Working knowledge of many programming and implementation languages.


ARM Cortex A series (AAE)


bash, ksh, csh, sh, tcsh



CoCentric SystemStudio

DesignCompiler, PhysicalCompiler


Doxygen, pod, nroff, pdf,




Linux (RedHat admin)

Mac OS 9, X


MS Office (Excel, PPT, Word)

nfs, samba, ftp, rsync

Perl, Perl5

PrimeTime, Motive

rcs, cvs, subversion, git

SignalScan, Undertow, DeBussy

ssh, pgp, gpg, crypt, des

Sun OS, Solaris

SystemC, SCV, TLM 2.0

SystemVerilog, UVM


Test Compiler, TetraMax

Unix utilities awk, sed, grep

Vera, e-Specman

Verilog-XL, NC, VCS, MTI

Verilog1995, 2001,


Vivado HLS

Windows 3.1, NT, 2000, XP



As a consultant, I have worked with many companies including (alpha):

      AMD in Austin-TX, ARM in Austin-TX, Cadence Design in San Jose-CA, Compaq Computers in Austin-TX, Conexant in San Diego-CA, Datacube in Boston-MA, Forte Design in San Jose-CA, FreeScale in Austin-TX, Hewlett-Packard in Vancouver-WA and Barcelona-Spain LSI Logic in Austin-TX, Lightfleet Corp. in Camas-WA Lockheed-Martin in Dallas-TX, Mentor Graphics in Portland-OR, Nortel Networks in Ottawa-ON and Belfast-Ireland, Northrup-Gruman in San Diego-CA, PMC Sierra in Vancouver-BC, Teradyne in Beaverton-OR, Texas Instruments in Dallas-TX, Houston-TX, San Diego-CA and Bangalore-India. Tundra Semi in Canata-ON


Doulos America, Austin, TX - Aug 2011 to present

Senior Member of Technical Staff responsible for teaching a variety of skills related to the electronics industry (e.g. SystemVerilog verification, SystemC modeling, and UVM methodology). I work hard to ensure my students fully understand the subject matter they endeavor to learn.

XtremeEDA USA Corporation, Austin, TX - Jul 2008 to Aug 2011

President of US subsidiary responsible for leading team. ESL (Electronic System Level design) Practice Leader responsible for guiding ESL technology within the company. After a merger of ESLX Inc with XtremeEDA Corporation of Canada, I led the ESL practice. During this time I contributed to SystemC standardization in the Open SystemC Initiative’s (OSCI), authored two editions of SystemC: From the Ground Up (Springer), helped start the North American SystemC Users’ Group, and became chairperson of the OSCI Language Working Group (LWG).

Eklectically Inc. DBA ESLX Inc., Austin, TX - Jan 2003 to Jun 2008

Chief Technical Officer and Consultant founding a new consulting venture. Focussed on effective hardware, software co-design methodologies including higher levels of modeling and reuse. Co-author of SystemC: From the Ground Up

Synopsys Inc., Austin, TX - Apr 2001 to Dec 2002

Staff Professional Consultant assigned to teaching, methodology, behavioral compiler technology and general design/verification issues for customers. Worked with clients performing verification using SystemC co-simulating with VHDL, synthesis of IP including Power Compiler, DFT Compiler, Physical Synthesis and TetraMax technologies.

Qualis Design Corp., Austin, TX - Oct 1997 to Mar 2001

Principal Engineer assigned to teaching, methodology, behavioral compiler technology and general design/verification issues for customers. Worked with clients on large (8M gates) designs in multiple areas of technology (IC test, T1 communications, multimedia, ATM and graphics processing). Responsibilities ranged from methodology to implementation to verification. Aided clients understanding issues migrating from one simulator to another. Provided automated regression environments for both verification and synthesis. Taught numerous classes in Verilog HDL for both verification and synthesis. Received excellent evaluations from students. Learned Verisity's e Specman Elite for verification. Studied System C and Vera. Established the first remote office for Qualis in Austin, TX. Helped hire an excellent team. Participated in corporate planning and cultural dynamics.

Apple Computer Inc., Austin, TX - Dec 1994 to Oct 1997

Scientist assigned to Mutlti-media Design.

Hardware/ASIC design engineer on Set Top Box and Multi-media product development. Synthesized multi-media ASIC (0.65 micron CMOS 50K gate array 240PQFP 40MHz) including full scan test. Designing Video/Graphics ASICs. 100K+ embedded array using Synopsys Behavioral Compiler and synthesis tools. Design includes full scan and JTAG. Responsible for setup and maintenance of EDA environment (HP & Sun UNIX workstations).

Tandem Computers Inc., Austin, TX (acquired by Compaq) - Sep 1988 to Dec 1994

Staff Engineer assigned to S2 Integrity development, a fault-tolerant RISC based UNIX platform.

Assigned physical design of large ASIC (0.5 micron CMOS 200K cell-array 391CPGA 50MHz). Responsibilities included Synopsys synthesis, Cadence Preview floor planning, Synopsys test generation and back-end processing for vendor.

Provided key tools and advice to other four ASIC design groups on project. As project specific tool smith/ASIC advisor promoted, learned, taught and augmented a large set of heterogeneous CAE tools on Sun/HP workstations. Key player in development of ASIC design methodology. Tools included Verilog, Synopsys, Compass, Motive, Valid, Allegro, IKOS.

Major role in the development of a large ASIC (1 micron CMOS 50K gate-array 25MHz) using synthesized HDL methodology with full internal scan and JTAG boundary scan. Independently designed (on Dazix) a small ASIC and second source (1st pass success). Qualified Ethernet controllers. Implemented I/O interface including scan based PAL.

ROLM Corporation, Austin, TX (acquired by IBM and subsequently Siemens) - Nov 1981 to Sep 1988

Advisory Engineer assigned to Telephone Products R&D. Hardware/system engineer on ISDN product development.

Architect for large ASIC (10,000+ gate standard cell) project to cost reduce/enhance existing product. Developed DFT methodology.

Project Engineer/Project Engineer on product cost reduction effort, also Project/Design Engineer on new ASIC ( Application Specific Integrated Circuit) of 2,000+ gate standard cell with unqualified first time success. Proposed/architected highly successful RP244 product. Three patents granted.

Designed ASIC (1200 gates) using standard cell methodology had first time success. Substantial CAE (Daisy et al) experience. Directed university co-op students' projects. Investigated and directed implementation (MSI TTL) of several architectures for PBX data communications networking.

Designed and implemented firmware (Intel 8051) for data communications product used in all ROLM desktop products (Intel 8088 based). Designed telephone and data communications hardware (Intel 8051 & 80C49) for Cypress™; product (design was subsequently reused successfully in Cedar™; and Juniper™ products). Recognized as ROLM Outstanding Contributor 1985.

Data General Corporation, Austin,TX (acquired by Storage Technology and subsequently defunct) - May 1980 to Nov 1981

Engineer I assigned to alphanumeric CRT terminals R&D.

Worked on firmware (Motorola 6800 assy) for color alphanumeric terminal marketed as Dasher™; D280C. Designed software tool (Pascal) to aid use of redefineable character set feature in new terminals. Continuing engineering of advanced terminal (Motorola 6809 based). CAE (TEGAS) class.


  1. BulletBook “SystemC: From the Ground Up”, 1st (2003) & 2nd (2009) editions hardcover & paperback (also available in Japanese & Korean),

  2. BulletPaper "Avoiding Verilog Nightmares during Verification" SNUG Mar 2000,

  3. BulletPaper "Pushing the Limits with Behavioral Compiler" SNUG Mar 1999,

  4. BulletPaper "LOGSCAN: A Configurable Error Management Utility" SNUG Mar 1998,

  5. BulletPaper "Designing a 100-kgate Set-Top Box ASIC Using Behavioral Compiler with Verilog", Integrated System Design June 1996;

  6. BulletPatent 5,345,495 Data diagnostics with LEDs on the face of a telephone on 06Sep94;

  7. BulletPatent 5,008,902 Automatic Baud Rate Detection on 16Apr91;

  8. BulletPatent 4,928,306 Dynamically configurable telephone on 22May90


Rice University, Houston, Texas 1980 B.S.E.E. and B.A.C.S.

Emphasis in digital electronics and computer science. Minor in biomedical electrical engineering.

Additional course work.


Naturalized US Citizen. Passport current.


Scout Leader (Chaplain), Venturing Scout Advisor, Active member South Austin Church of the Nazarene; IEEE Computer Society (Secretary/Treasurer for 1981-2); Eagle Scout (Houston 1973)


Family, Scouting, Austin Habitat for Humanity, Interfaith Hospitality Network, Racial Justice, Home Computing (Macintosh), Bicycling/Exercising, Cooking, Camping/Backpacking, Astronomy